As a result, the number of CPU cycles spent processing each packet decreases by 16-84%. A prototype system based on the modified FreeBSD operating system shows that handoff reduces the number of instructions and cache misses on the host CPU. Handoff is trans- parent to the application, and the operating system may choose to offload connections to the network interface or reclaim them from the interface at any time. Using handoff, the operating system controls the number of offloaded connections in order to full y uti- lize the network interface without overloading it. However, full TCP offloading may degrade system performance because finite processing and memory resources on the network interface limit the amount of packet processing and the number of connections. Offloading can reduce computa- tion and memory bandwidth requirements for packet processing on the host CPU. Using this interface, the operating system can offload a subset of TCP connections in th e system to the network interface, while the remaining connections are processed on the host CPU. This paper presents a connection handoff interface between the op- erating system and the network interface. The test results show us that the applications can access the applied memory of kernel by mapping The main method we used is the combination of MMAP and PROC procedures, and at the end, we also introduce the implementation of test program and the test strategies. In this paper, we based on Linux (kernel version 2.6.11), by modifying its network device driver snull.c (attached in Linux Device Driver version 3), to implement the memory mapping between Linux kernel space to user application space. By working together with TOE technology, it can drop the communication delay effectively and save a lot of CPU cost. By DMA technology, network interface devices can store data packets into the address where it can be accessed directly by user application, the data packets copy operation is removed in kernel and reducing the data transmission path. Zero-copy means on any network node, during message transmission, there is no data copy among memory segments and all messages transmission are operated directly between user application space and outside of network through network interfaces. The error between the theoretical throughput (7.342 Mbps) and the measured throughput (7.5067 Mbps) was ∼2.24%. The measurement results indicate that the operating frequency, baud rate, data transfer rate, power consumption, processing delay, gate count, and chip size are 125 MHz, 115,200 Hz, 1 Gbps, 137 mW, 139.31 µs, 162,300, and 1.27 × 1.27 mm², respectively, at a power supply of 1.8 V and total FIFO queue of 10 kB. Furthermore, the large FIFO size enables the transmission of the maximum Ethernet packet length of 88 B and allows the latency of 51 clocks to be overcome. An application‐specific integrated circuit is proposed to increase the operation frequency of the two‐port–two‐port SI. The proposed SI, which is composed of an RS485 module, an Ethernet module, a transmitter manager, a receiver manager, and the manager first‐in–first‐out (FIFO) queue, not only increases the data transmission rate but also guarantees correct communication between two Ethernet modules and two RS485 modules. This study proposes a two‐port Ethernet and two‐port RS485 network serial interface (SI) for packet transformation and data transmission for computer‐to‐computer communication. Therefore, the system throughput achieves 7.11 Gbps that can deal with the traffic of Gigabit Ethernet in end system. The power consumption without SRAM is 7.21 mW. As the results of simulation, the speed of the chip is 227.2 MHz and the area is 0.936 * 0.733 mm2. Besides, because of the Gigabit NIC support Jumbo Frame mostly, we figure out the packet size adopted 9 Kbyte from which the performance is higher than the traditional 1.5 KByte. The checksum hardware just calculates packet header instead of whole packet with payload for UDP packet so that it can reduce the processing clock cycles for multimedia delivery. In this paper, we propose a UDP/IP ASIC to accelerate networking multimedia transmission. The CPU workload is heavy and the processing of network protocol task is the bottleneck. The network traffic has rapidly increased that produces amount of interrupts, memory copies and checksum calculation in end system. With the growing of internet service, multimedia applications require higher communication speed.
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